1. Field of the Invention
The present invention relates to a method and apparatus of testing and analyzing a complementary metal oxide semiconductor (CMOS) integrated circuit.
2. Description of the Related Art
Japanese Unexamined Patent Publication (Kokai) No. 8-271584, Japanese Unexamined Patent Publication (Kokai) No. 9-211088, U.S. Pat. No. 5,392,293, U.S. Pat. No. 5,519,333, and U.S. Pat. No. 5,889,408 disclose testing (IDDQ testing) using a drain-to-drain quiescent power supply current (IDDQ) of a CMOS integrated circuit.
In IDDQ testing, measures the quiescent power supply current of a CMOS integrated circuit, is measured, and a good or defective of the CMOS integrated circuit is determined by using the measured current. Note that a CMOS integrated circuit under test is also called a device under test (DUT).
A quiescent power supply current IDDQ includes a leakage current (intrinsic leakage current) flowing even in a good device and a defect current caused by a defect. That is, a quiescent power supply current IDDQ, (hereinafter also called a quiescent power supply current IQ) can be expressed by the summation of the intrinsic quiescent power supply current IF and defect current ID and can be shown by the following formula (1):
IQ=IF+ID xe2x80x83xe2x80x83(1) 
The intrinsic leakage current IF can be expressed by the summation of the leakage current (FET leakage current) IT generated due to the structure of a metal oxide semiconductor field effect transistor (MOSFET) and the leakage current (circuit leakage current) caused due to a circuit operation.
The circuit leakage current is generated by an analog circuit, pull-up current, bus collision, etc. Generation of the circuit leakage current is however avoided when IDDQ testing for measuring the quiescent power supply current IQ and therefore it can be disregarded. Therefore, the following formula (2) can represent the defect current ID:
ID=IQxe2x88x92IT xe2x80x83xe2x80x83(2) 
In the IDDQ testing, the FET leakage current IT of the CMOS integrated circuit under test is unknown and therefore estimated by some method or another. The good or defect of the CMOS integrated circuit is judged by using the measured quiescent power supply current IQ.
The main defect current ID in the quiescent power supply current IQ is current generated by internal shorts among gates, sources, drains, and well of the FET and a bridging between interconnection patterns. The value of the defect current ID depends on the power supply voltage and equivalent resistance value.
FIG. 1 is a graph of the relative frequency distribution of the maximum IDDQ(the maximum value of the quiescent power supply current IQ) in two types of integrated circuits as an example. The maximum IDDQ of an abscissa is broken down into 0 to 100 xcexcA, 100 to 200 xcexcA, . . . , 700 to 800 xcexcA, and 800 xcexcA or more.
The effective gate length Leff of the type A and B CMOS integrated circuits is 0.5 xcexcm. A maximum IDDQ of more than 30 xcexcA is shown. The distribution shown in FIG. 1 substantially corresponds to the distribution of the defect current ID.
Further, A. E. Gattiker and W. Maly, xe2x80x9cToward Understanding xe2x80x98Iddq-Onlyxe2x80x99 Failsxe2x80x9d, in Int. Test Conf., pp.174-183, IEEE, 1998, states that there is an indirectly generated defect current, in addition to the defect current generated directly by the bridging. This indirect defect current is generated because when a potential of a signal line falls between the power-supply voltage and the ground potential for some reason or another, the p type MOSFET and n type MOSFET driven by this signal line become on in state at the same time, and a penetration current flows.
It is necessary to apply a different voltage to the two ends of a bridge forming a defect in order to cause generation of the defect current ID.
Since it is impossible to set the potential required for all presumed failures all at once, a test signal of a test pattern prepared by an automatic test pattern generator (ATPG) or a test signal of a test pattern for a function test is applied and the quiescent power supply current IQ measured when a terminal becomes the necessary potential. Note that a measurement point for measuring the quiescent power supply current IQ is called as a strobe (strobe point).
The strobe point (defect detection strobe point) which can detect a defect differs according to the cause of the defect.
Since bridging between the power supply line for supplying a power supply voltage VD and a ground line has no relation with the potential of the signal line, the defect is detected at all strobe points and the defect current becomes the same.
Note that there are few defect detection strobe points which can detect bridging of interconnections between cells. Further, the number of defect detection strobe points which can detect a short of the MOSFET in the cell is a levels between the two.
According to A. Keshavarzi, K. Roy, and C. F. Hawkins, xe2x80x9cIntrinsic Leakage in Low Power Deep Submicron CMOS ICsxe2x80x9d, in Int. Test Conf., pp. 146-155, IEEE, 1997; A. Ferre and J. Figueras, xe2x80x9cOn Estimating Bounds of the Quiescent Power Supply Current for IDDQ Testingxe2x80x9d, in VLSI Test Sym., pp. 106-111, IEEE, 1996; and P. C. Maxwell and J. R. Rearick, xe2x80x9cEstimation of Defect-Free IDDQ in Submicron Circuits Using Switch Level Simulationxe2x80x9d, in Int. Test Conf., pp. 882-889, IEEE, 1998, the leakage current (EFT leakage current) IT of a defect-free normal MOSFET can be classified based on the ON/OFF state of the MOSFET, the current path, etc.
FIG. 2 is a graph showing a classification of the leakage current of a MOSFET.
FIG. 2 shows a feeding power route, causes of occurrence, conduction conditions, and an approximation formula of the leakage current with respect to cases L1, to L3.
In the case L1, the feeding power route is between a well and base (substrate), the cause of occurrence is an inverse bias of a pn junction, and the conduction condition is an ON state.
In the case L2, the feeding power route is between a drain and well, the cause of occurrence is the inverse bias of the pn junction, and the conduction condition is an OFF state.
In the case L3, the feeding route is between the drain and source, the cause of occurrence is a weak inverse, and the conduction condition is an OFF state.
The leakage current of the case L1 is always generated if the well and base are inverse biases and is constant regardless of the strobe (strobe point).
The leakage current of the case L2is generated in a case where the MOSFET is in an OFF state and the drain thereof is connected to the power supply line and/or the ground line.
The leakage currents of the case L3 is generated in a case where the MOSFET is in an off state and the drain and the source thereof are connected to the power supply line and/or the ground line.
If the leakage currents of the cases Li (i =1 to 3) in each MOSFET in a CMOS integrated circuit are averaged for each case, the leakage currents LN1 and LN1 in per n type MOSFET and p type MOSFET are found.
The FET leakage current IT can be expressed by the following formula (3) using the numbers NN1 and NP1 of the n type MOSFETs and the p type MOSFETs in which the leakage current of the case L1 has been generated:                               I          T                =                              ∑                          F              =              1                        3                    ⁢                      (                                                            N                  Ni                                xc3x97                                  I                  Mi                                            +                                                N                  Pi                                xc3x97                                  I                  Pi                                                      )                                              (        3        )            
FIG. 3 is a chart illustrating the distribution of the maximum IDDQ in an CMOS integrated circuit and shows the frequency distribution for every 0.1 xcexcA. The effective gate length Leff of the CMOS integrated circuit is 0.5 xcexcm.
In FIG. 3, a CMOS integrated circuit having a maximum IDDQ of less than 1 xcexcA is judged as good and a CMOS integrated circuit having a maximum IDDQ of 1 xcexcA or more is judged as defective.
Note that the broken line shows a curve of an average value of 0.2 xcexcA and a standard deviation "sgr" of 0.14 xcexcA. In a good CMOS integrated circuit having a maximum IDDQ of below 1 xcexcA, the distribution of the FET leakage current is the normal distribution or similar to the normal distribution.
Note that if 1(≈0.2÷6xc3x970.14) xcexcA of exactly 6"sgr" from the average value is made the maximum FET leakage current assuming a variation in current between lots, a quiescent power supply current IQ above that is considered to be due to a defect. That is, 1 xcexcA is the threshold value of judgement of good or defective.
When the threshold value of judgement of good or defective is set to 1 xcexcA in this way, a defect current of up to a maximum of 0.9 (=1 to 0.1) xcexcA in a CMOS integrated circuit having an FET leakage current of 0.1 xcexcA in the chart of FIG. 3 is missed.
Note that in the chart of FIG. 3, defective CMOS integrated circuits having a maximum IDDQ of 1 to 4 xcexcA are substantially uniformly distributed. It is assumed that they are distributed at a range below 1 xcexcA as well. However, the number of defective CMOS integrated circuits of less than 1 xcexcA is small, so the failure to catch such defective CMOS integrated circuits in the testing can be disregarded.
FIG. 4 is a graph of the distribution of the FET leakage current in two good CMOS integrated circuits. Note that in a good CMOS integrated circuit, the defect currents ID is considered of a degree which can be disregarded and so the quiescent power supply current IDDQ of a good CMOS integrated circuit is considered the FET leakage current. The effective gate length Leff of the two CMOS integrated circuits LSI-1 and LSI-2 is 0.25 xcexcm.
The abscissa of FIG. 4 shows the consecutive numbering of the strobe points (strobe number), while the ordinate shows the magnitude of the FET leakage current at each strobe point.
The FET leakage current of the CMOS integrated circuit LSI-1 changes up to xc2x110 xcexcA about approximately 73 xcexcA, while the FET leakage current of the CMOS integrated circuit LSI-2 changes up to xc2x15 xcexcA about approximately 29 xcexcA.
FIG. 5 is a chart of the relative frequency distribution of an FET leakage current at all 800 strobe points in the CMOS integrated circuit LSI-1 and LSI-2 of FIG. 4. The abscissa is graduated into units of 10 xcexcA.
In the chart of FIG. 5, two different variations are seen.
The first variation is the variation among strobe problems in the same CMOS integrated circuit as seen from 25 to 35 xcexcA.
The second variation is the variation between CMOS integrated circuits such as the center of frequency distribution being around 73 xcexcA in the CMOS integrated circuit LSI-1 and around 29 xcexcA in the CMOS integrated circuit LSI-2.
FIG. 6 is a chart illustrating the relative frequency distribution of FET leakage current in a case where the average value of the quiescent power supply current in a CMOS integrated circuit (average IDDQ) is considered the FET leakage current. The chart of FIG. 6 illustrates the distribution of 32 good CMOS integrated circuits randomly sampled from two lots. The current is widely distributed from 0 to 350 xcexcA.
The above judgement of good or defective using as the threshold the estimated maximum value of the FET leakage current is liable to miss catching many defects.
As one example, if 85xcexcA is made the threshold value in the chart of FIG. 5, the occurrence of a defect current of 60 (=85 to 25) xcexcA in a CMOS integrated circuit LSI-1 having an FET leakage current of 25 xcexcA cannot be detected.
In this way, in the above IDDQ testing measuring the quiescent power supply current of a CMOS integrated circuit and judging that circuit to be defective when the measured value is above a threshold, as described in T. W. Williams, R. H. Dennard, and R. Kapur, xe2x80x9cIddq Test: Sensitivity Analysis of Scalingsxe2x80x9d, in Int. Test Conf., pp. 786-792. IEEE, 1996, sometimes accurate judgement is difficult.
For example, this is because, when the interconnection pattern of the CMOS integrated circuit is fine, the leakage current of a MOSFET (FET leakage current) increases exponentially along with the fineness. Specifically, this is because the FET leakage current in the case L3 increases exponentially due to the shortening of the effective gate length Leff and the fall in the threshold voltage Vth.
Therefore, various methods for reducing FET leakage current during IDDQ testing have been proposed.
One method of reducing the FET leakage current in IDDQ testing is to lower the FET leakage current when strobing so as to reduce the threshold. The low power supply voltage method, low temperature measurement method, and a well bias method are known for this.
The low power supply voltage method uses the fact that the leakage current falls by the approximation formulas of cases L1 to L3 shown in FIG. 2 when lowering the power supply voltage VD. However, since the power supply voltage can only be reduced to an extent where the circuit does not malfunction, the rate of reduction of the FET leakage current is low.
Further, several milliseconds (ms) are necessary to change the power supply voltage VD before and after strobing. The test cost is increased along with this increase of testing time.
Moreover, according to A. E. Gattiker and W. Maly, xe2x80x9cToward Understanding xe2x80x98Iddq-Onlyxe2x80x99 Failsxe2x80x9d, in Int. Test Conf., pp. 174-183, IEEE, 1998, there are cases where the fault penetration current disappears when lowering the power supply voltage VD and this may lead to defects being missed in the testing.
This method uses the fact that the FET leakage current falls by the approximation formula of the case L3 shown in FIG. 2 when lowering the operating temperature.
The lower limit temperature is determined by the guaranteed reliability and the cost of the test system for maintaining the low temperature and test system. The limit in civilian use low temperature maintaining systems is about 0"ogr"C, so the rate of reduction of the FET leakage current is low. Further, the expense of the system and its running costs pile up and increase costs.
The well bias method is described in a paper of A. Keshavarzi, K. Roy, and C. F. Hawkins, xe2x80x9cIntrinsic Leakage in Low Power Deep Submicron CMOS ICsxe2x80x9d, in Int. Test Conf., pp. 146-155, IEEE, 1997.
The leakage current falls by the approximation formulas of the cases L1 to L3 shown in FIG. 2 when the threshold voltage Vth is raised. Further, the threshold voltage rises when a bias voltage is applied between the source and well.
In this method, since interconnections are added to apply the bias voltage, the chip of the CMOS integrated circuit on the chip is increased and the cost rises.
Further, the rate of reduction of the leakage current is very susceptible to variations in the effective gate length Leff, so the FET leakage current fluctuates along with increasing miniaturization.
On the other hand, methods have been proposed for judging good or defective or detecting defect current in a state with a large FET leakage current. For example, there are the signature analysis method, delta method, and upper and lower limit method.
However, in these methods, it suffers from that detection of defect currents less than the variation of the FET leakage current among strobes is impossible, defects where the same defect current is generated at all the strobe points miss being caught, and estimation of the defect current is difficult.
The signature analysis method is disclosed in a paper of A. E. Gattiker and W. Mary, xe2x80x9cCurrent Signaturesxe2x80x9d, in VLSI Test Sym., pp. 112-117. IEEE, 1996.
In this method, since the measured quiescent power supply currents are rearranged in order of magnitude and good or defective is judged based on existence of any sharp steps, it is not too well suited for mass production.
The delta method is described in a paper of C. Thibeault, xe2x80x9cOn the Comparison of xcex94IDDQ and IDDQ Testingxe2x80x9d, in VLSI Test Sym., pp. 143-150, IEEE, 1999.
In this method, defective CMOS integrated circuits are separated by the amount of change of the quiescent power supply current, so a large amount of statistical processing is necessary. Therefore, this method is not too well suited to a mass production process.
The upper and lower limit method is disclosed in U.S. Pat. No. 5,914,615, Jun. 1999, B. Chess, xe2x80x9cMethod of Improving the Good or Defective and Efficiency of Iddq Testingxe2x80x9d.
In this method, the upper and lower limit are set according to the average value of the measured quiescent power supply currents and are used to detect defective CMOS integrated circuits.
However, since variations among CMOS integrated circuits and variations among strobes are not differentiated, error sometimes occurs in the upper limit value and lower limit value calculated from the average value of the quiescent power supply currents.
A first object of the present invention is to provide a method and apparatus of testing a CMOS integrated circuit capable of judging the good or defective of a CMOS integrated circuit having a large quiescent power supply current and large variations.
A second object of the present invention is to provide a method and apparatus of analyzing a CMOS integrated circuit capable of detecting a defect current of a CMOS integrated circuit having a large quiescent power supply current and large variations.
According to a first aspect of the present invention, there is provided a method of testing a CMOS integrated circuit comprising the steps of: applying a test signal to a CMOS integrated circuit under test and measuring a quiescent power supply current at part or all of the strobe points among a predetermined plurality of strobe points; and judging the good or defective of the CMOS integrated circuit under test based on average value ratios of quiescent power supply currents of the plurality of strobe points calculated in advance for a good CMOS integrated circuit, the measured values at the part or all of the strobe points, and the average value of the measured values.
Preferably the step of judging the good or defective based on the average value ratios, the measured values, and the average value comprises the steps of calculating defect current estimated value PDj: IQjxe2x88x92Rjxc3x97Iq corresponding to the strobe points based on the average value ratios Rj of the quiescent power supply currents at the plurality of strobe points, the measured values IQj at the part or all of the strobe points, and the average value Iq; and judging the good or defective of the CMOS integrated circuit under test based on the calculated defect current estimates PDj and allowable error E of the measured values of the quiescent power supply current.
Alternatively, the step of judging good or defective based on the defect current estimated value PDj and the allowable error E judges the CMOS integrated circuit under test as a defect when an absolute value of a calculated defect current estimate PDJ is larger than an absolute value of the allowable error E.
Alternatively, the step of judging good or defective based on the defect current estimates PDj and the allowable error E comprises the steps of calculating a variation rate PSTQ=Iqxc3x97(Rb-RS)/(IQb/- IQs) when each of a plurality of absolute values of the plurality of defect current estimated value PDJ corresponding to all of the strobe points is not more than the absolute value of the allowable error E and of judging the CMOS integrated circuit under test as a defect when the variation rate PSTQ is greater than 1. Here, Rb is the biggest average value ratio among the average value ratios Rj, IQb is the measured value of the strobe point corresponding to the biggest average value ratio Rb, Rs is the smallest average value ratio among the average value ratios Rj, and IQs is the measured value of the strobe point corresponding to the smallest average value ratio Rs.
In the latter case, the step of judging good or defective based on the defect current estimated value PDj and the allowable error E may further comprise a step of judging the CMOS integrated circuit under test as good when the variation rate PSTQ is less than 1.
Preferably, the allowable error E of the measured quiescent power supply current is whichever of a product (ERxc3x97Iq) of a maximum error rate ER among error rates ERj of average value ratios Rj at the plurality of strobe points and the average value Iq and of a maximum measurement error EM has a larger absolute value.
Preferably, the average value is defined as an arithmetic average value of the measured values at part or all of the strobe points.
Alternatively, the average value is defined as ratio (IQ1/R1) between a measured quiescent power supply current IQ1 at a predetermined strobe point of the part or all of the strobe points and the average value ratio R1 of the quiescent power supply current at the predetermined strobe point.
In this case, preferably the step of judging good or defective based on the average value ratios, the measured values, and the average value comprises the steps of calculating defect current predictions PQ1j=IQjxe2x88x92Rjxc3x97(IQ1/R1) corresponding to the strobe points based on the average value ratios Rj of the quiescent power supply currents at the plurality of strobe points, the measured values IQj at the part or all of the strobe points, and the ratio(IQ1/R1) and judging good or defective based on the calculated defect current predictions PQ1j and the allowable error E of the measured values of the quiescent power supply current.
More preferably, the step of judging good or defective based on the defect current predictions PQ1j and the allowable error E comprises a step of judging the CMOS integrated circuit under test as a defect when an absolute value of a calculated defect current prediction PQ1j is larger than an absolute value of the allowable error E.
In the above case, preferably, the allowable error E of the measured quiescent power supply current is whichever of a product (ERxc3x97IQ1/R1) of a maximum error ratio ER among a plurality of error ratios ERj of the average value ratios Rj of the quiescent power supply current at the plurality of strobe points and the ratio (IQ1/R1) and of the maximum measurement error EM has the larger absolute value.
In the above case, alternatively, the step of judging good or defective based on the average value ratios, the measured values, and the average value comprises the steps of calculating an upper limit threshold IQU=(1+fxc3x97"sgr"R)xc3x97 IQ1/R1 based on the average value ratio R1 of the quiescent power supply current at the predetermined strobe point, the ratio (IQ1 /R1), and a constant f of 4 to 7; and judging the CMOS integrated circuit under test as a defect when a measured quiescent power supply current is larger than the upper limit threshold IQU, where "sgr"R is the square root of the average value of (Rjxe2x88x921)2 at the plurality of strobe points.
Here, preferably the step of judging good or defective based on the average value ratios, the measured values, and the average value further comprises the steps of calculating a lower limit threshold IQL=(1xe2x88x92fxc3x97"sgr"R)xc3x97IQ1/R1; judging the CMOS integrated circuit under test as a defect when a measured value is below the lower limit threshold IQL; and judging the CMOS integrated circuit under test as good when each of the measured values at the part or all of the strobe points between the lower limit threshold IQL and the upper limit threshold IQU.
Here, alternatively, the value of the constant f is 5 to 6.
In the above case, alternatively, the step of judging good or defective based on the average value ratios, the measured values, and the average value comprises the steps of calculating a lower limit threshold IQL=(1xe2x88x92fxc3x97"sgr"R)xc3x97IQ1/R1 based on the average value ratio R1 of the quiescent power supply current at the predetermined strobe point, the ratio (IQ1/R1), and a constant f of 4 to 7 and judging the CMOS integrated circuit under test as a defect when the measured quiescent power supply current is smaller than the lower limit threshold IQL, where "sgr"R is the square root of the average value of (Rjxe2x88x921)2at the plurality of strobe points. Here, preferably, the value of the constant f is 5 to 6.
In the above case, alternatively, the predetermined strobe point comprises a first strobe point of the part or all of the strobe points.
According to the present invention, there is also provided an apparatus for testing a CMOS integrated circuit comprising: a means for applying a test signal to a CMOS integrated circuit under test and measuring a quiescent power supply current at part or all of the strobe points among a predetermined plurality of strobe points; and a means for judging the good or defective of the CMOS integrated circuit under test based on average value ratios of quiescent power supply currents of said plurality of strobe points calculated in advance for a good CMOS integrated circuit, the measured values at the part or all of the strobe points, and the average value of the measured values.
According to a second aspect of the present invention, there is provided a method of analyzing a CMOS integrated circuit, comprising the steps of applying a test signal to a CMOS integrated circuit under test and measuring a quiescent power supply current at a predetermined plurality of strobe points; calculating defect current estimated values PDj=IQjxe2x88x92Rjxc3x97Iq corresponding to the strobe points based on average value ratios Rj of quiescent power supply currents at the plurality of strobe points calculated in advance for a good CMOS integrated circuit, measured values IQj at the plurality of strobe points, and an average value Iq of the measured values; calculating a summation PDSUM of negative value defect current estimated value PDJ among the calculated defect current estimated values PDJ; calculating a summation RSUM of the average value ratios Rj for the strobe points corresponding to the negative value defect current estimated value PDj among the plurality of strobe points; and calculating an absolute value |PDSUM /PSUM| of a ratio of the summation PDSUM of the defect current estimated value PDj and the summation RSUM of the average value ratios Rj.
Preferably, the method further comprises the steps of calculating first current values IDj=PDj+Rj+Rjxc3x97|PDSUM/RSUM| for strobe points corresponding to a positive value defect current estimated value PDj among the plurality of strobe points and detecting first current values which are larger than an absolute value of an allowable error E of a measured value of the quiescent power supply current among the calculated first current values IDj as defect current values.
Alternatively, the method further comprises the steps of calculating a second current value ID=(1xe2x88x921/PSTQ)xc3x97Iq based on a variation rate PSTQ=Iqxc3x97(Rbxe2x88x92Rs)/(IQbxe2x88x92IQs) when each of the calculated first current values IDj is not more than the absolute value of the allowable error E and detecting that each of the measured values at the plurality of strobe points includes a defect current value indicated by the second current value ID when the second current value ID is larger than the absolute value of the allowable error E, where Rb is the biggest average value ratio among the average value ratios Rj, IQb is the measured value at the strobe point corresponding to the biggest average value ratio Rb, Rs is the smallest average value ratio among the average value ratios Rj, and IQs is the measured value at the strobe point corresponding to the smallest average value ratio Rs.
Here, preferably, the method further comprises the step of detecting that each of the measured values at the plurality of strobe points does not include a defect current value when the second current value ID is not more than the absolute value of the allowable error E.
Preferably the allowable error E of the measured quiescent power supply current is whichever of a product (ERxc3x97Iq) of a maximum error rate ER among error rates ERJ of average value ratios Rj of the quiescent power supply current at the plurality of strobe points and the average value Iq and of a maximum measurement error EM has a larger absolute value.
Preferably, the average value is defined as an arithmetic average value of the measured values at the plurality of strobe points.
Preferably, the average value ratios of the quiescent power supply currents at the plurality of strobe points are ratios between the plurality of measured values obtained by applying the test signal to a good CMOS integrated circuit and measuring the quiescent power supply current at a plurality of strobe points and the average value of the plurality of measured values which are then in turn averaged for a plurality of good CMOS integrated circuits or for more than a plurality of good CMOS integrated circuits.
According to the present invention, there is provided an apparatus for analyzing a CMOS integrated circuit, comprising: a means for applying a test signal to a CMOS integrated circuit under test and measuring a quiescent power supply current at a predetermined plurality of strobe points; a means for calculating defect current estimated values PDj=IQjxe2x88x92Rjxc3x97Iq corresponding to the strobe points based on average value ratios Rj of quiescent power supply currents at the plurality of strobe points calculated in advance for a good CMOS integrated circuit, measured values IQj at the plurality of strobe points, and an average value Iq of the measured values; a means for calculating a summation PDSUM of negative value defect current estimated value PDj among the calculated defect current estimated values PDj; a means for calculating a summation RSUM of the average value ratios Rj for the strobe points corresponding to the negative value defect current estimated values PDj among the plurality of strobe points; and a means for calculating an absolute value |PDSUM/PSUM of a ratio of the summation PDSUM of the defect current estimated value PDj and the summation RSUM of the average value ratios Rj.
In both the method and apparatus of testing and the method and apparatus of analyzing a CMOS integrated circuit according to the present invention, preferably, the test signal has a plurality of test patterns and the method further comprises a step of switching test patterns between adjacent strobe points of the plurality of strobe points.
That is, in the method and apparatus of testing a CMOS integrated circuit according to the present invention, since use is made of average value ratios of quiescent power supply currents at a plurality of strobe points calculated in advance for a good CMOS integrated circuit and an average value of measured values of the quiescent power supply currents, it is possible to determine the distribution of quiescent power supply currents in a good CMOS integrated circuit with reference to the average value of the quiescent power supply currents and therefore learn the ranges which measured values can take when the CMOS integrated circuit under test is a good one from the average value ratios of the quiescent power supply currents and the average value of the measured values.
For example, the method and apparatus calculates defect current estimates PDj=IQjxe2x88x92Rjxc3x97Iq based on the average value ratios Rj of quiescent power supply currents at the plurality of strobe points, the measured values IQj, and the average value Iq of the measured values.
By multiplying the average value Iq of the measured values by an average value ratio Rj, it is possible to calculate the expected value of a quiescent power supply current IDDQ in a case where the CMOS integrated circuit under test is a good one. By subtracting this expected value (Rjxc3x97Iq) from a measured value IQj, it is possible to obtain a defect current estimate.
Note that a defect current estimate PDj can be predicted from a defect current IDj at that strobe point, the summation of the defect currents at all strobe points, the total number m of the strobe points, and the average value ratio Rj, so a value not depending on the size of a measured value of the quiescent power supply current can be obtained.
Further, the method and apparatus for example calculates defect current predictions PQ1j=IQjxe2x88x92Rjxc3x97IQ1/R1 based on the average value ratios Rj of the quiescent power supply currents at a plurality of strobe points, the measured values IQj, and the ratio (IQ1/R1).
By multiplying the ratio (IQ1/R1) corresponding to the prediction of the average value of the measured values and an average value ratio Rj, it is possible to calculate an expected value of the quiescent power supply current IDDQ in a case where the CMOS integrated circuit under test is a good device. By subtracting this expected value (IQ1xc3x97Rj/R1) from a measured value IQj, it is possible to obtain a defect current prediction.
Note that the defect current prediction PQ1j can be projected from the defect currents IDj and ID1 at strobe points and the average value ratios Rj and R1, so a value not depending on the size of the measured value of the quiescent power supply current can therefore be obtained.
The method for example calculates an upper limit threshold IQU=(1+fxc3x97"sgr"R)xc3x97IQ1/R1 based on the average value ratio R1 of the quiescent power supply current at the predetermined strobe point, the ratio (IQ1/R1), and a constant f of 4 to 7.
By multiplying the ratio (IQ1/R1) corresponding to the prediction of average value of the measured values by (fxc3x97"sgr"R) relating to the standard deviation of the average value ratios R1, it is possible to calculate the range of distribution of the quiescent power supply current IDDQ in the case where the CMOS integrated circuit under test is good. By adding this range (fxc3x97"sgr"Rxc3x97IQ1/R1) and the ratio (IQ1/R1), it is possible to obtain the upper limit threshold.
"sgr"R can be calculated from an average value ratio R1 and the total number m of the strobe points, so a value not depending on the measured value of the quiescent power supply current can be obtained.
The method for example calculates the lower limit threshold IQL=(1xe2x88x92fxc3x97"sgr"R)xc3x97IQ1/R1 based on the average value ratio R1 of the quiescent power supply current at the predetermined strobe point, the ratio (IQ1/R1), and a constant f of 4 to 7.
By multiplying the ratio (IQ1/R1) corresponding to the prediction of the average value of the measured values by (fxc3x97"sgr"R) relating to the standard deviation of the average value ratios R1, it is possible to calculate the range of distribution of the quiescent power supply current IDDQ the case where the CMOS integrated circuit under test is good. By subtracting this range (fxc3x97"sgr"Rxc3x97IQ1/R1) from the ratio (IQ1/R1), it is possible to obtain the lower limit threshold.
"sgr"R can be calculated from the average value ratio R1and the total number m of the strobe points, so a value not depending on the measured value of the quiescent power supply current can be obtained.
The method of analyzing a CMOS integrated circuit according to the present invention calculates defect current estimates PDj=IQjxe2x88x92Rjxc3x97Iq based on the average value ratios Rj of quiescent power supply currents at a plurality of strobe points, measured values IQj, and an average value Iq.
By multiplying the average value Iq of the measured values by an average value ratio Rj, it is possible to calculate the expected value of a quiescent power supply current IDDQ in the case where the CMOS integrated circuit under test is good. By subtracting this expected value (Rjxc3x97Iq) from a measured value IQj, it is possible to obtain a defect current estimate.
By calculating the absolute value |RDSUM/RSUM| of a ratio between the summation PDSUM of the negative value defect current estimated value PDj and the summation RSUM of the average value ratios RJ for the strobe points corresponding to the negative value defect current estimates PDJ, it is possible to obtain a variation xcex94Iq showing the difference between the average value of the measured values and the average value of FET leakage currents.
As explained above, according to the methods of testing and analyzing a CMOS integrated circuit of the present invention, it is possible to detect and analyze defect currents even with a CMOS integrated circuit with a large quiescent power supply current and large variations.